Honored Contributor
Honored ContributorDear Experts:
Thank you for your help. I think I should first give more detail information here. so you can know what wrong with me more exactly. I am a beginer in using niosII. we have not purchase any development kit, but fortunately, we have a stratix FPGA board for other applications. there is a Stratix EP1S20F780 and four chips of Cypress CY7C1021CV33(64K X 16 bits) on it. the FPGA is connected to these 4 SRAMs. the SRAMs are asynchrous SRAMs, which has ADDRESS(16), DATA(16), CE_n(1), WE_n(1), CS_n(1), CE_n(1), BHE_n(1), BLE_n(1) , OE_n(1) and VCC, GND ports. we dived these 4 SRAMs to two groups, each group is consists of 2 chips. alougth all SRAMs are 16 bits of width, but we use 2 chips to width expand each group to 32 bits of width. the FPGA connect with SRAMs ADDRESS(2 groups: A0[15:0], A1[15:0]), DATA(2 groups: DATA0[31:0], DATA1[31:0]), OE_n(2 groups: OE_n0, OE_n1), WE_n(2 groups: WE_n0, WE_n1). we connect all remain SRAMs ports to fixed levels, either VCC or GND. CS_n connect to sgnal GND, always select; BHE_n and BLE_n connect to signal GND too, so, all 4 Bytes are always selected. When I first touch nios, I use FPGAs onchip memories as nios' memory, and run the helloword program. it success! But the onchip memory's capacity is limited. so, I try to use the SRAMs on my board. 1st, I add IDT71V416 and avlon tri-state bridge and run Helloword program, it did not work. 2nd, I write a Verilog HDL module to list all the used ports of the SRAM, but in this way, I can not make it a tri-state slave. because alougth i define the DATA ports as inout in the Verilog file, but in the SOPCB, I found these DATA ports remain input ports. so, the SOPCB give following error message: avalon_tristate_slave_0: slave has write signals but no data signal avalon_tristate_slave_0: slave has read signals but no data signal avalon_tristate_slave_0: slave must have a read or write interface or support interrupts So, my second attempt also failed. My 3rd attempt did not use a verilog HDL file, I just open the Create new component, add signals and select interface in the create new component window. I added 4 signals. they are DATA, ADDRESS, READ_n, WRITE_n. after generate the system, I created a new project, in the project's top module, I wrote: assign ADDRESS = NIOS_SYSTEM's ADDRESS[17:2]; assign OE_n = READ_n after all these steps, I programmer the FPGA(using the .sof file), run helloword program, the result is: nios2-terminal: starting in terminal mode (using ctrl + C to eixt) no "hello" message displayed. by the way, I use the byteblaster not a USB cable. thank you all. gong xuechun
