About external SRAM

try the following:

add the ram as user logic

(remark one userlogic for both ram chips,

this is necessary to get one block of memory for system library properties)

I think your address width is 17 (128k=2*64k*32bit)

PORTNAME WIDTH DIRECTION SHARED TYPE

address 17 input yes address

write_n 1 input yes write_n

read_n 1 input yes read_n

data 32 inout yes data

chipselect_n 1 input --- chipselect_n

be_n 2 input yes byteenable_n remark: not needed

add external logic in top.bdf (one not and two ors's) to generate the

two different CS signals

SRAM_CS0_N = SRAM_CS or A16

SRAM_CS1_N = SRAM_CS or (not A16)