about component made by user logic

Ok, in your timing volations look at the source and destination to determine where these critical paths are (I'm guessing it will be between the FIFO and IUL).

Also just to be sure all those blocks are driven with the clock from the PLL correct?

Have you tested these two combinations first to make sure they meet requirements?

-- Custom Logic I -> FIFO

-- FIFO -> Custom Logic II

But if I had to guess where the problem is it would most likely be a timing mismatch between the FIFOs and the IUL (but find out where the critical path is first before attempting a fix). Once you know the critical path then you can focus your efforts on the interface causing the problems. Also with the FIFOs make sure that the IUL timing is what your FIFO needs, take a look at the time diagrams for the IUL in SOPC builder and verify that will not break your FIFO (I usually use that timing information to simulate my external hardware before dropping the NIOS core into the system).