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Altera_Forum's avatar
Altera_Forum
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21 years ago

about component made by user logic

hello, anyone encounter this problem that a component made by user logic can't run with nios system that has comprised ram and flash and so on? who can give me some suggesti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Yeah, I have chosen all the possible optimizations for the project. Although the Nios and peripherals run in asynchoronizing mode, only one system clock be input here.

Yeah there are some worse slacks between such interfaces. How can I do some modifications? Some are not important because they are not run in synchoronizing mode, I think. Right? So which one is the first to be constrained?

Thanks