Honored Contributor
Honored Contributoroh ok, then that's the cause of the problems. When you add additional hardware to the NIOS, sometimes (well often actually) you impact the timing of the NIOS as well.
First I would try to use some of the built in optimizations from Quartus to bring up the fmax. Analysis & Synthesis Settings --> Optimization Technique --> Speed | ----> Synethesis Netlist Optimizations --> Perform WYSIWYG re-synthesis Fitter Settings --> Standard Fit | ----> Physical Synthesis Optimizations --> Turn them all on Those are a few to try (if you are just under the fmax you want you probably don't need all these turned on), just remember your compile time gets longer with some of these turned on. Also you have set fmax to 100MHz in your timing options right? What are your negative slack times (the red ones), and associated frequencies of those (if any). Another question I have is, do you use the same system clock in your IUL hardware as the NIOS? (If you have multiple clock domains you need to be careful with your design).
