about component made by user logic

Thanks for your information.

We finish the custom hardware with an address space for data transmission. And it works perfectly in accordance with the timing requirements on testing.

I use the default option for fMax setting but clear the default value. I think it will make the fMax equal to the system clk. Then I calculate the max worse delay from some important pins to others. And then setting the corresponding value for IUL and SRAMs thru .ptf file. It can wok now. Further verification will be tested soon.

Thanks.