about component made by user logic

Yes when you add your own hardware to an SOPC system you can have some negative effects on your timing (especially if you do a custom instruction). I would just set some fmax for your system to allow the compiler to route accordingly, also there are other settings that you can enable in Quartus that will slow down the compiler but it may give you better timing results.

It's possible that the timing that you have set for your custom interface is not enough for your custom hardware that you have added to your system. Another question I have is do you have an address space in your custom hardware or it just a simple read and write interface? (PIO may be what you want to use then). If you do have addresses out there then make sure you decode those properly to ensure that you are latching your data properly. To determine what is causing timing problems you look at the worst case paths and look at the source and destination points, and its usually enough information to determine the problem (since you are looking at the data path causing the problem).

There is another thing to keep in mind and that's multi-cycle registers. If you have logic that depends on data that Quartus can not anticipate properly (like external I/O for example), then it may be assuming that the register only has one clock cycle to latch whereas they may have two or more in reality. Before jumping the gun on that idea though make sure you understand that concept and read up on the multi-cycle settings for Quartus.

My last question: Is this a school project or is it for work? (i.e. do you have to keep most of this disclosed or can your design be shown, because if I saw the design I could probably figure out the problem)