Forum Discussion
Altera_Forum
Honored Contributor
21 years agoAre you using data cache by any chance (f core)? If so, when you do your read/write to it you need to bypass the data cache. If you read or write without doing this the data may get cached and the next access may come straight from the cache instead of the external logic that you made.
IOWR_32DIRECT(base, offset, data) // to write bypassing cache int IORD_32DIRECT(base, offset) // to read bypassing cache And if that's not the cause let us know. Cheers