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Honored Contributor
Honored ContributorA problem with on-chip FIFO memory and NIOS II
Hi there, I am pretty new to NIOS II, but used to work hard in the previous months :) I stumbled upon a strange behaviour with the On-chip FIFO memory. Namely, I have, as a tryout, a system ...
Altera_ForumHonored Contributor
Honored ContributorThanks, I can see that the SGDMA did not read out the FIFO since the descriptors were not placed in a memory mastered by SGDMA MM interface...
But... the other problem remains, if the FIFO is empty after software reset the first four writes are lost, i.e. immediately after a write to FIFO an empty interrupt is generated and FIFO gets a kind of flushed. It is not a case if the FIFO was not empty at the software reset. The SGDMA is idle at that time, the handle has not even been created before the FIFO is loaded.
