A Newbie's struggle

Scott

Thanks for the path to the boot loader!

The SDRAM tests were performed using the bit 31 cache bypass - in any event, the address test writes the full 16MB with unique values before reading it back for verification.

From your experience, I suspect a hardware problem with SDRAM burst access not covered by my tests. From other postings here, I gather that the Nios II does not achieve back-to-back reads on its data bus, but does on its instruction bus. My tests would not detect this.

I believe that the DMA is latency aware. Perhaps it would be a sufficiently challenging test to catch problems. I'll try.