Forum Discussion
Altera_Forum
Honored Contributor
21 years agoA Newbie's struggle
I am sure the answer is simple but, I am running out of time... I am running Quartus II V4.2 with Nios II V1.1. My proprietary target system is based on the Cyclone EP1C2Q240C7, an EPCS ch...
Altera_Forum
Honored Contributor
21 years agoYou have an EPCS controller but no EPCS device populated? When the system is set to boot from the EPCS controller then the bootloader within the controller starts copying the user region of the EPCS device (which you don't have) to the target (you want SDRAM).
As for whether the downloader (Nios II IDE) can run code out of SDRAM, that's how all the Nios II reference boards run code when the IDE downloads to them. To verify, if you run your code out of on-chip memory you are able to access SDRAM properly? My other question is, why do you have an EPCS controller if you don't populate the EPCS device? I would have the exception address in SDRAM, and the reset address...... doesn't matter right now since you are trying to download via the Nios II IDE. I would probably stick the reset location in SDRAM right now because you are pointing it at a bootloader current and that may be causing you problems (I don't know why though).