A new processor

Hi SimKnutt,

I believe you mean designing custom processors from fpga logic and memory.

i.e. designer decides that their work is too complicated and slow for HDL and that software(nios...) is too slow for it. So they decide to go for custom oriented processors inside fpga.

The problem is getting new tools and compilers to move from C to your custom processor level. So it needs a real industrial weight.

Hope you are well.

kaz

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Hi SimKnutt,

I believe you mean designing custom processors from fpga logic and memory.

i.e. designer decides that their work is too complicated and slow for HDL and that software(nios...) is too slow for it. So they decide to go for custom oriented processors inside fpga.

The problem is getting new tools and compilers to move from C to your custom processor level. So it needs a real industrial weight.

Hope you are well.

kaz

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The file attachment was generated by the software that takes C code input, generates the memory contents, and simulates the hardware.

I believe that the word 'compiler' generally means: Parse, generate assembly code or some other intermediate language, then generate machine language which everyone assumes is just one of many instruction sets which only differ slightly.

The point is that C statements are either assignments or statements that are essentially test a condition/relation then do one of two things. Also the number of cpu registers is very important and a lot of effort is spent allocating registers. All registers are in a ram block in this design so the access time is the same as if in dedicated hardware. There can be as many "registers" as the application needs.

Probably the C++ question will come up. The point is what you described above. We are talking about the situation when doing a function in HDL is difficult, but time constraints do not permit a software implementation. Therefore, I contend that C++ support is not required and that a subset of the C standard is all that's necessary. We are trying to make things a bit easier than HDL.

As an aside, my program uses objects and clocking like the actual hardware operates. I run in debug mode to see what the hardware does at each clock. With an understanding of the design, a user can see what the hardware is doing at each clock at a functional level. This is part of the package because I had to have it in order to design the thing.

Thanks, kaz I am well and appreciate the comment. Be well also.

Hi SimKnutt,

Thanks for your comments. Your thinking is certainly valid and interesting.

However, the trend of the new generation industry is towards automating

complex functionality to higher levels like C or just blocks(simulink) then the converting the work from the high level functionality down to HDL or direct to fpga bitstream bypassing HDL.

There is heavy investment in that area between Mathworks,Xilinx and Altera...etc

This approach maintains the speed of direct hardwiring.

The new generation engineers have yet to prove that these tools work practically...

I have a lot of trouble understanding how a designer can ever comprehend the complexities being created. multicore and parallel programming are full speed ahead with very little explanation of how well it will work. Here's my take on multicore, Intel saw maybe half the processor cucle were spent waiting so dual core came along and improved performance(how much?). Well if 2 is good, many, many will be better. But what if two used up all the cycles, did 3 and 4 steal cycles from 1 and 2 causing them to slow down? I have read in some forum that multicore actually does run slower for unknown reasons.

Sure parallel programming is a part of supercomputers, but look at the number of processors.

In the case you mentioned if something doesn't work quite right, does the designer have to use timing simulation to debug logic never before seen?

While I wish them luck, I fear it may just be an academic exercise. There was a Microsoft research into why FPGAs are so fast compared to a processor and they found the processor spent a lot of time fetching instructions. They missed the point that you mentioned, parallelism in the FPGA. My design uses that parallelism very much because several rams, counters, etc are used in parallel. Please think about the demo code running in 48 cycles and maybe just guess at what it would take in HDL. That is the margin of performance to be gained at whatever cost.

My design could be put to use quickly while that research could continue in parllel.

Thanks again, I enjoy a good discussion.

Ok, then you mean several parallel small processors. The degree of parallelism scalable in the core. Sounds worth evaluating performance with HDL.

If successful, it should defeat HDL and simulink and DSP all at same time.

I wonder if there is a study in this area.

Usually there has been an RTOS that doles out processor time to all the functions.There are interrupts and context switch overhead involved. If it is economical to have parallel dedicated processors, then that goes away also.

I am not sure "The degree of parallelism scalable in the core." is exactly accurate. Each processor derives its performance from parallelism and each is the same, just different physical sizes. The next degree of parallelism is then from multiple processors running in parallel. So now we use the inherent FPGA function very much as HDL does. Also I think the overall operation is simplified.

I don't know enough about simulink and DSP.

Seems like the whole business is still based on the original concepts that are being pushed to the limits as chip density increases.

By the way, I do realize that some communication between processors is required. It should be something like "Here go do this" and "OK, I'm done".

As far as studies, I think there has been a lot of "I need something else, and I will try anything available that sounds possible."

Hi SimKnutt

Your project sounds interesting for research but is not practical in an industrial environment. At the end it remains a fact that todays engineers have to follow the market tools and cores. Design complexity is gone too far for any personal flavoring. We are all having a miserable time with vendor documentations of their own tools with no channel to express our frustrations apart from these lovely sanctuary of forums.

We also have hard time adjusting to the changes the vendors constantly make to their tools. It is a new type of tyrrany I am afraid but with common goal, to make profit for companies so we may pay our rent.

from vhdl to verilog to the dead AHDL, ABLE,...C, Qbasic, TCL, TimeQuest, Ruby, DOS, m files, simulink fun and the mosaic of converters back and forth.. from xilinx package of scattered tools to Altera's semi-integrated Quartus, to Modelsim, to ...infinity of tools and their web subversions and you name it. We need some poetry to express our frustration.

And the design environment;chaotic masses of entangled wires and connectors on everbody's desk, some desks never seen the daylight in their life. The tons of codes and modules scattered in tons of folder and subfolder names, I have never never successfully and painlessly reused any piece of inhouse work and preferred to start from a scratch.

Wishing you all the success and my apologies.

Hi kaz, you may never see this because "the message is too short" came up after I spent all this time trying to edit the quote of your reply. Maybe I need to add a smiley!

It did not come out as planned, but maybe it's the thought that counts.

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Hi SimKnutt

Hi kaz As you know, I am not an active "today" engineer, but I would like to add a comment or two.

Your project sounds interesting for research but is not practical in an industrial environment. At the end it remains a fact that todays engineers have to follow the market tools and cores. Design complexity is gone too far for any personal flavoring. We are all having a miserable time with vendor documentations of their own tools with no channel to express our frustrations apart from these lovely sanctuary of forums.

Is the only requirement that a tool be on the market? I suppose "lemons" don't exist

but in a later paragraph you list some has-beens. By the way, I remember when Ron Waxman came to my office to talk about a new way to describe hardware. At the time we used Automated Logic Diagrams but the government did not want the volume of paper.

Later I think he went to work on VHDL. To this day, I cannot see how a description language became a quasi programming language.

We also have hard time adjusting to the changes the vendors constantly make to their tools. It is a new type of tyrrany I am afraid but with common goal, to make profit for companies so we may pay our rent.

I wonder how much the computer science guys are taught about hardware. If they don't know the physics/logic of a latch and the concept of clocking, well you get what you get.

from vhdl to verilog to the dead AHDL, ABLE,...C, Qbasic, TCL, TimeQuest, Ruby, DOS, m files, simulink fun and the mosaic of converters back and forth.. from xilinx package of scattered tools to Altera's semi-integrated Quartus, to Modelsim, to ...infinity of tools and their web subversions and you name it. We need some poetry to express our frustration.

Maybe you need a tool that lets you see what it is doing.

And the design environment;chaotic masses of entangled wires and connectors on everbody's desk, some desks never seen the daylight in their life. The tons of codes and modules scattered in tons of folder and subfolder names, I have never never successfully and painlessly reused any piece of inhouse work and preferred to start from a scratch.

But it sounds like you are surviving with "outhouse" tools. You truly are superhuman if you can continue to start from scratch and effectively utilize the millions and millions of circuits on future chips.

I am sorry that you consider this a research project. I have just analyzed how the looping and decision statements work, recognized the analogy between function blocks and OOP objects.

The source file for my code is a little over 2k lines, including spaces and comments. The one catch is that it is not for free.

Wishing you all the success and my apologies.

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