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Altera_Forum
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16 years ago

A new processor

I am asking for comments on my project. It is a custom component used with SOPC builder, its purpose is to allow many more time critical functions to be programmed in C. When these functions are d...
Altera_Forum's avatar
Altera_Forum
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16 years ago

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Hi SimKnutt,

I believe you mean designing custom processors from fpga logic and memory.

i.e. designer decides that their work is too complicated and slow for HDL and that software(nios...) is too slow for it. So they decide to go for custom oriented processors inside fpga.

The problem is getting new tools and compilers to move from C to your custom processor level. So it needs a real industrial weight.

Hope you are well.

kaz

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The file attachment was generated by the software that takes C code input, generates the memory contents, and simulates the hardware.

I believe that the word 'compiler' generally means: Parse, generate assembly code or some other intermediate language, then generate machine language which everyone assumes is just one of many instruction sets which only differ slightly.

The point is that C statements are either assignments or statements that are essentially test a condition/relation then do one of two things. Also the number of cpu registers is very important and a lot of effort is spent allocating registers. All registers are in a ram block in this design so the access time is the same as if in dedicated hardware. There can be as many "registers" as the application needs.

Probably the C++ question will come up. The point is what you described above. We are talking about the situation when doing a function in HDL is difficult, but time constraints do not permit a software implementation. Therefore, I contend that C++ support is not required and that a subset of the C standard is all that's necessary. We are trying to make things a bit easier than HDL.

As an aside, my program uses objects and clocking like the actual hardware operates. I run in debug mode to see what the hardware does at each clock. With an understanding of the design, a user can see what the hardware is doing at each clock at a functional level. This is part of the package because I had to have it in order to design the thing.

Thanks, kaz I am well and appreciate the comment. Be well also.