Honored Contributor
Honored Contributor<div class='quotetop'>QUOTE </div>
--- Quote Start --- 1) can be solved very easy if you call the signals as altera recomments them[/b] --- Quote End --- Thanks for the naming. I can't believe I worked without knowing this, and it's right there in the docs http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif I also needed 'ats' for addressing external memory chip. Gladly this is a 16 bits (actually 18) device. I'm using the tri-state-bridge component with it as well. Can that solve your 8 bit memory mode problem? <div class='quotetop'>QUOTE </div> --- Quote Start --- 5) ... i add this file to a quartus project and do the analyze there until is does not mention any error or warning then i go back to the sopc[/b] --- Quote End --- I have Xilinx tools installed as well and easy to verify HDL in there. 6) Too bad that a SOPC system doesn't generate a SOPC component. Difficult to do that manually too because of the lack of proper prefixes. <div class='quotetop'>QUOTE </div> --- Quote Start --- 7) how should such a fifo behave ?[/b] --- Quote End --- Such a FIFO should be configurable much like the MegaWizard for lpm_fifo_*. Width, depth, synchronization/clocks, and status output to a slave control port. Interrupt to signal an under-/overflow and it could do avalon handshake to pause input when it's full. <div class='quotetop'>QUOTE </div> --- Quote Start --- 9) there is no external memory model to implement a external tristate bus to connect external devices[/b] --- Quote End --- tri-state-bridge can be used for external memories I think. 11) and how to get the base addresses for slave interfaces in some other HDL file instead of system.h? I could parse the pts file and output some HDL code for it... 12) Component Editor HDL analysis hangs on global (gls_*) signals ending with "clk"
