64bit ddr2 conflit with lan91c11

Ok I see. This issue is starting to become more familiar and if I remember correctly there isn't a nice workaround.

So.... in your situation what I recommend you do is as follows:

1) Make sure to use the SDRAM in full rate mode

2) Make sure to use the HP2 implementation of the SDRAM controller

3) Set the local burst size of the SDRAM controller to 1

4) For the Nios II master connections to the SDRAM set the arbitration share to 8*

* if your data cache line size is 4 bytes/line use 1, if your data cache line size is 16 bytes/line use 4.

This will allow you to avoid clock crossing and burst adaptation. The single word accesses by the CPU will get condensed into off-chip bursts for you by the memory controller.

Alternatively you could also try Qsys. Qsys doesn't support native addressing and just treats native slave ports as 32 bits wide dynamic ports. So I suspect this issue can't show up in Qsys.