64bit ddr2 conflit with lan91c11

thanks for your reply, but that will go back to the first problem. my beginning plan is to make NIOS2 and DDR2 controller run in the same clock domain. but if I don't add cross clock bridge, before generation, no any base address confict. while in the half process of generation, a lot of strange base address conflits happen. if I change DDR2 controller local if to 32 bits, then no any conflicts during generation. so I think you are right it's caused by native addressing with slaves wider than the masters. but as I know, SOPC build should adap this automatically. So how to get rid of it if the ddr2 local IF has to be 64bit? and by the way, I also test this conflicts on cycloneIII_3c120_dev_niosII_standard_sopc example in the kits of Quartus91, same with my desgin.