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Altera_Forum
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11 years ago

4-NIOS design, only processor 0 fails to boot from flash at power-on

I have a design with 4-NIOS processors. A single flash part is used for storing the FPGA image as well as NIOS FW image. At power on, 3 of the NIOS processors successfully load from flash and beg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Are you referring to delaying the waitrequest signal? Where did you modify and how long was the delay added? Interested to find out your solution on this.