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Altera_Forum
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11 years ago

4-NIOS design, only processor 0 fails to boot from flash at power-on

I have a design with 4-NIOS processors. A single flash part is used for storing the FPGA image as well as NIOS FW image. At power on, 3 of the NIOS processors successfully load from flash and beg...
Altera_Forum's avatar
Altera_Forum
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10 years ago

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Curious, do you know how long is your power-on reset versus reset button asserted?

Are you using EPCS flash controller provided in Qsys (EPCS/EPCQx1 Serial Flash Controller)?

What version of Quartus are you using?

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The issue was that the NIOS processor was allowed to read from the flash too quickly following reset. The flash part has a minimum reset time after power-on that was not being followed. The arbitration logic was changed to delay the grant signal back to the NIOS processor.