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Altera_Forum
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11 years ago

4-NIOS design, only processor 0 fails to boot from flash at power-on

I have a design with 4-NIOS processors. A single flash part is used for storing the FPGA image as well as NIOS FW image. At power on, 3 of the NIOS processors successfully load from flash and beg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

How are you sequencing the nios boot?

Only one of the nios can access the flash at any one time.

So if you are using the Altera EPCS boot code you need to have all but one of the nios power up with the 'soft reset' asserted.

After each nios finishes booting it should take the next nios out of reset.

Alternatively make one nios responsible for loading all the code/data and put the reset vectors for the other directly into the loaded code.