4 bit universal shift register using vhdl

This thread may help

http://www.alteraforum.com/forum/showthread.php?p=86911

--- Quote Start ---

no i dont need anyone to do my work for me, i just need a rough idea of how i can start to implement it into VHDL. thanks

--- Quote End ---

You already were given a 'rough idea'. Now it's up to you to come back and ask a more specific question based on what you've learned about shift registers, VHDL, or whatever topic you actually need help with. Fishing for someone to give up and write your code for you is pathetic. Specifically, what is it about a shift register or VHDL has you baffled?

Kevin Jennings

i have made a start to it but i dnt know if i am on the right track.

here is the code so far

entity universal_shift_register is

Port ( SIR, SIL, CLK, RST, : in STD_LOGIC;

D : in STD_LOGIC_VECTOR (3 downto 0);

Q : out STD_LOGIC_VECTOR (3 downto 0));

end universal_shift_register;

architecture Behavioral of universal_shift_register is

begin

process (CLK)

Variable: REG: std_logic_vector (3 downto 0);

if clk'event and clk= '1' then

if

end Behavioral;

give me feedback please. i also have (s0 s1) as inputs but i am not sure if i am supposed to incule them and how

--- Quote Start ---

i have made a start to it but i dnt know if i am on the right track.

here is the code so far

entity universal_shift_register is

Port ( SIR, SIL, CLK, RST, : in STD_LOGIC;

D : in STD_LOGIC_VECTOR (3 downto 0);

Q : out STD_LOGIC_VECTOR (3 downto 0));

end universal_shift_register;

--- Quote End ---

You're missing S1 and S0 inputs...add them

--- Quote Start ---

architecture Behavioral of universal_shift_register is

begin

process (CLK)

Variable: REG: std_logic_vector (3 downto 0);

if clk'event and clk= '1' then

if

end Behavioral;

give me feedback please. i also have (s0 s1) as inputs but i am not sure if i am supposed to incule them and how

--- Quote End ---

- S1 and S0 are listed in the definition so why wouldn't you need them?

- The process will also need to have RST in the sensitivity list since the description says that RST is an asynchronous reset input. If RST had been a synchronous reset, then RST would not be in the sensitivity list. Besides the sensitivity list, then you'll need to add code to support RST (as well as the other inputs) like this...

signal REG: std_logic_vector (3 downto 0);

...

process (CLK)

if rising_edge(clk) then

.. Here you add your code for computing REG as a

.. function of SIR, SIL, S1, S0

end if;

if (RST = '1') then

.. Here you define what REG should be set to when it is reset

end if ;

end process;

Q <= REG; -- Set the output of the entity

Note: With REG as a variable, you wouldn't be able to set the Q output outside of the process. If you tried to set 'Q <= REG' inside the process, then there would be an extra clock cycle delay that would probably not be desired.

Kevin Jennings

thanks alot Kevin Jennings, that was great help, i was able to finish the coding. but i may need some help on carrying out a Test Bench for it please.

here is the final coding

entity USR is

Port ( D : in STD_LOGIC_VECTOR (3 downto 0);

CLK, RST : in STD_LOGIC;

SIR, SIL : in STD_LOGIC;

S :in STD_LOGIC_VECTOR (1 downto 0);

Q : out STD_LOGIC_VECTOR (3 downto 0));

end entity USR;

architecture Behavioral of USR is

begin

process(CLK, RST) is

variable REG : std_logic_vector(3 downto 0);

begin

if (RST = '0') then

reg := (others => '0');

elsif rising_edge(clk) then

case S is

when "11" =>

REG := D;

when "01" =>

REG := SIR & REG(3 downto 1);

when "10" =>

REG := REG(2 downto 0) & SIL;

when others =>

null;

end case;

end if;

Q <= REG;

end process;

end architecture;

Is there any reason you've used a variable? why didnt you just assign Q wherever reg is? its bad practice to assign a signal outside of a clocked branch.

As for the test bench - what problems do you need help with?