32-bit loade performed as 4 8-bit loads

I noticed that gcc seems to be turning my 32-bit loads in to 4 8-bit loads.

The C++ code is:

struct Data

{

inline int read() volatile { return m_data; }

inline volatile char* getDataAddr() volatile { return reinterpret_cast<volatile char*>(&m_data); }

private:

volatile int m_data;

}_PackedType data;// Data

a call to data.read() will generate the following assembly:

ldbuio r2,0(r3)

andi r4,r2,255

ldbuio r2,1(r3)

andi r2,r2,255

slli r2,r2,8

or r4,r2,r4

ldbuio r2,2(r3)

andi r2,r2,255

slli r2,r2,16

or r4,r2,r4

ldbuio r2,3(r3)

andi r2,r2,255

slli r2,r2,24

or r2,r2,r4

this seems to be the case with or without optimization.

I guess my question is, why wouldn&#39;t the compiler just have generated one of the ldw instructions rather than perform 4 memory reads, a bunch of shifts and a bunch of ands?

Thanks