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Altera_Forum's avatar
Altera_Forum
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13 years ago

2 Nios II with autonomous peripherals !

Hi All,

I am been using a NIOS II core in my application for performing some activites. Now i wish to add another NIOS II to do a independent activity in the same application, which i am currently doing using VHDL block.

I went through the document on multiple processors from altera but it concentrates on making a shared memory application. in case of separate memories for the processors can anyone let me know how to proceed with the qsys and the software ?

Regd Software i currently first JTAG the Quartus Code. Then Run the C code from Eclipse as Hardware and download it using JTAG cable.

Thanks in advance. This is an urgent requirement please help.

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  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hey.... I got the system to work. This is wat i did....

    > The NIOS II Processor's Reset vector was pointing to EPCS device and Exception Vector was also Pointing to EPCS device

    > Program memory was pointing to SRAM

    > I Changed the Exception vector to an Onchip memory and now the flash programmer is working fine.

    Any idea why it needs to be defined like this ?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The exception vectors need to be in a RAM because they are initialized by the software just before jumping to main(). If you put them to a ROM then the initialization software can't write the correct ISR vector and the CPU would probably crash at the first raised interrupt.

    I'm glad you got it to work!