--- Quote Start ---
originally posted by raghuraman@Oct 13 2005, 07:11 AM
i am using the cypress 32bit mem megafunction and have used a doubled clock for memory access. --- Quote End ---
I'm not sure what you mean by "doubled clock" (DDR-style data on both clock edges, or simply doubled clock frequency?).
That said, you probably don't want the Cypress 32 bit memory component. You should create a custom component with no HDL files, make its slave an Altera Tristate Bus type, with memory addressing (instead of "native/register" addressing), and add whatever signals you need to hook up to the memory (CE=chipselect, WE=write, OE=read, A[...]=address, D[...][]=data). Then add it and an Altera Tristate Bridge to your design, hook it all up, and you should be good.
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