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Altera_Forum's avatar
Altera_Forum
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19 years ago

16 bit SRAM

Dear all,

I have a problem that is maybe already seen by one of you:

I have generated a NIOS core with a 256Kx16 bit SRAM interface. The SRAM module is connected to the avalon tri-state bridge.

Address = (0-17)

Data = (0-15)

WRn = 1 bit

RDn = 1 bit

CSn = 1 bit

BHEn=1 bit

BLEn = 1 bit

The generation of the nios core completes without errors. But after I have finished my design fitting .. I get following warning

SRAM_Address(0) is synthezised away

Any idea why?... Is the address mapping between the avalon bridge and the sram module wrong?

Regards

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by karel van haver@Dec 1 2006, 12:07 PM

    dear all,

    i have a problem that is maybe already seen by one of you:

    i have generated a nios core with a 256kx16 bit sram interface. the sram module is connected to the avalon tri-state bridge.

    address = (0-17)

    data = (0-15)

    wrn = 1 bit

    rdn = 1 bit

    csn = 1 bit

    bhen=1 bit

    blen = 1 bit

    the generation of the nios core completes without errors. but after i have finished my design fitting .. i get following warning

    sram_address(0) is synthezised away

    any idea why?... is the address mapping between the avalon bridge and the sram module wrong?

    regards

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19768)

    --- quote end ---

    --- Quote End ---

    Read the building memory subsystems (http://www.altera.com/literature/hb/qts/qts_qii54006.pdf) section in the SOPC Builder handbook. Look at table 9-1... You&#39;re welcome to either modify the existing Europa-based (Perl HDL generation) SRAM component or generate your own using the Component Editor/Builder.

    Best Regards,

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by slacker+dec 1 2006, 04:13 pm--><div class='quotetop'>quote (slacker @ dec 1 2006, 04:13 pm)</div>

    --- quote start ---

    <!--quotebegin-karel van haver@Dec 1 2006, 12:07 PM

    dear all,

    i have a problem that is maybe already seen by one of you:

    i have generated a nios core with a 256kx16 bit sram interface. the sram module is connected to the avalon tri-state bridge.

    address = (0-17)

    data = (0-15)

    wrn = 1 bit

    rdn = 1 bit

    csn = 1 bit

    bhen=1 bit

    blen = 1 bit

    the generation of the nios core completes without errors. but after i have finished my design fitting .. i get following warning

    sram_address(0) is synthezised away

    any idea why?... is the address mapping between the avalon bridge and the sram module wrong?

    regards

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19768)

    --- quote end ---

    --- Quote End ---

    Read the building memory subsystems (http://www.altera.com/literature/hb/qts/qts_qii54006.pdf) section in the SOPC Builder handbook. Look at table 9-1... You&#39;re welcome to either modify the existing Europa-based (Perl HDL generation) SRAM component or generate your own using the Component Editor/Builder.

    Best Regards,

    - slacker

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=19769)</div>

    [/b]

    --- Quote End ---

    Slacker,

    Thanks a lot for the spec sheet. So, my thought that the mapping between the SRAM address and the tri state address pinning wasn&#39;t correct and is indeed explained in the spec sheet.

    So, instead of connecting SRAM A0 pin to tri-state-bridge-address0, I should connect SRAM A0 to tri-state-bridge-address1 and keep tri-state-bridge-address0 unconnected.

    Regards

    Karel