16 bit SRAM

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originally posted by karel van haver@Dec 1 2006, 12:07 PM

dear all,

i have a problem that is maybe already seen by one of you:

i have generated a nios core with a 256kx16 bit sram interface. the sram module is connected to the avalon tri-state bridge.

address = (0-17)

data = (0-15)

wrn = 1 bit

rdn = 1 bit

csn = 1 bit

bhen=1 bit

blen = 1 bit

the generation of the nios core completes without errors. but after i have finished my design fitting .. i get following warning

sram_address(0) is synthezised away

any idea why?... is the address mapping between the avalon bridge and the sram module wrong?

regards

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Read the building memory subsystems (http://www.altera.com/literature/hb/qts/qts_qii54006.pdf) section in the SOPC Builder handbook. Look at table 9-1... You&#39;re welcome to either modify the existing Europa-based (Perl HDL generation) SRAM component or generate your own using the Component Editor/Builder.

Best Regards,

- slacker