16 bit sram timing question

16 bit sram timing question

QUARTUS 5.0 NIOS 5.0

I have problems with the timing of an sram chip on a custom board.

I don't know if it is some problem with reflections or something else.

i use ISSI IS61LV25616AL 256k x 16

NIOS [A18..A1] -> SRAM [A17..A0]

userlogic is setup as following:

Bus Interface Type: Avalon Memory Slave

PORT NAME | Width | Direction | Shared | Type

address | 18 | input | yes | address

write_n | 1 | input | yes | write_n

read_n | 1 | input | yes | read_n

writedata | 16 | inout | yes | data

chipselect_n | 1 | input | --- | chipselect_n

be_n | 2 | input | yes | byteenable_n

when I select timing in interface to userlogic and change "Wait"

e.g. Wait=2 it shown writen = 2cycles low, i think it should show 3

cycles low( one normal write cycle and two wait)

when i select:

setup=0 cycles

wait=0 cycles

hold=0 cycles

and check the timing with the scope for the following byte ,word and

dword accesses, then

- there are unnecessary read cycles in case of 8 and 16 bit read

- the dword 32 bit access has only one write strope and changes

address within strobe ?

the following show the timin g on the scope:

setup:0 wait:0 hold:0

(one X is 10ns)

BYTE(8bit) WRITE/READ (stb/ldbu)

CS XX__XXXX__XXXX__XXXX

WR XX__XXXXXXXXXXXXXXXX

RD XXXXXXXX__XXXX__XXXX

BE1 __XX____XX____XX____

BE0 ______________XX____

why second read access ?

WORD(16bit) WRITE/READ (sth/ldhu)

CS XX__XXXX__XXXX__XXXX

WR XX__XXXXXXXXXXXXXXXX

RD XXXXXXXX__XXXX__XXXX

BE1 ______________XX____

BE0 ______________XX____

why second read access ?

DWORD(32bit) WRITE/READ (stw/ldw)

CS XX____XX__XXXX__XXXX

WR XX____XXXXXXXXXXXXXX

RD XXXXXXXX__XXXX__XXXX

A0 ____XX________XX____

BE1 ____________________

BE0 ____________________

CS and WR are both low for 40ns ?

only one write access for two 16 bit words ?

is this timing normal ???

which documentation is actual up to date for avalon bus timing ?