16-bit shift left 2 register in VHDL

Ok, so I have a shift register (code below). But I need a shift left 2 register. So would I simply put "reg <= reg (14 downto 0) & '0' & '0';" ? Or do I need to do the shift process twice? I need help ASAP...any help would be great.

entity shiftreg is

Port

(

en : in STD_LOGIC;

clock : in STD_LOGIC;

reset :in std_logic;

data_i : in STD_LOGIC_VECTOR (15 downto 0);

shift : in STD_LOGIC;

data_o : out STD_LOGIC

);

end shiftreg;

architecture Behavioral of shiftreg is

signal reg: std_logic_vector (15 downto 0);

begin

process (clock, en,reg,reset)

begin

if reset<='1' then

reg<=data_i;

elsif (clock'event and clock <='1' ) then

if (en <='1') then

reg <= data_i;

elsif (en<='1' and shift<='1') then

reg <= reg (14 downto 0) & '0';

end if;

end if;

end process;

data_o <= reg (15);

end Behavioral;