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Altera_Forum
Honored Contributor
Honored Contributor_regs.h files...
Hi All,
I wondering how I want to access my custom hardware and create this _regs.h file. For information, my custom hardware using 128-bit Avalon bus and I need 128-bit register as the interface to the hardware. # define IORD_ALTERA_AVALON_PWM_CLOCK_DIVIDER(base) IORD(base, 0) # define IOWR_ALTERA_AVALON_PWM_CLOCK_DIVIDER(base, data) c# define ALTERA_AVALON_PWM_CLOCK_DIVIDER_MSK (0xFFFFFFFF)# define ALTERA_AVALON_PWM_CLOCK_DIVIDER_OFST (0) Above is the example from PWM tutorial. what the meaning of 0 in the IORD(base, 0) and IORD(base, 0). Is'nt the offset for the register? If I design with 128-bit register, so what the value for this? Still 0 or other value? Thank you...2 Replies
Altera_ForumYes the 0 is an offset.
Note that registers should be set up as "registered" mode, hence the first register would be at offset 0, the second at offset 4 (in a 32 bit system), and so on. I suspect that you will need a 128-bit register that's written using 4 writes of different 32-bit segments, the last write then committing the full 128 bits.- Altera_Forum
thank you buddy.. but i'm still confuse.. what did you mean with 4 write? isn't the timing for avalon slave change to 4 inside the Component Editor?
so the example become like this... # define IORD_ALTERA_AVALON_PWM_CLOCK_DIVIDER(base) IORD(base, 0) # define IOWR_ALTERA_AVALON_PWM_CLOCK_DIVIDER(base, data) IOWR(base, 0, data)# define ALTERA_AVALON_PWM_CLOCK_DIVIDER_MSK (0xFFFFFFFF)# define ALTERA_AVALON_PWM_CLOCK_DIVIDER_OFST (0) # define IORD_ALTERA_AVALON_PWM_DUTY_CYCLE(base) IORD(base, 4) # define IOWR_ALTERA_AVALON_PWM_DUTY_CYCLE(base, data) IOWR(base, 4, data)# define ALTERA_AVALON_PWM_DUTY_CYCLE_MSK (0xFFFFFFFF)# define ALTERA_AVALON_PWM_DUTY_CYCLE_OFST (0)
