New Contributor" Downloading ELF process failed" Cyclone V GT Development board.(5CGTFD9EF35C7)
I am trying to access DDR3 memory using Quartus 18.1 subscription edition on Cyclone V GT Development board.(5CGTFD9EF35C7). I have used nios processor for programming purpose. I have interconnected all the required components (on chip memory, nios processor, DMA controller,
JTAG UART and external LED, DDR3, clock) using platform designer and set parameters of all components.I have used 100 MHz on board clock frequency oscillator to access DDR3 memory whose minimum data rate frequency is 300 MHz.After assigning pins to all input output port, I have compiled my design. My design compiled successfully and I have programmed my FPGA board by sof file.When I am trying to launch my nios processor to read/write on DDR3 memory, I stuck somewhere and got error " Downloading ELF process failed". I have rechecked my design, all the
pin assignment, reset and clock signal but still not able to identify exact issue of failure of launching of elf file on nios processor.
Kindly provide any solution
I have attached my qsys file (platform designer interconnect diagram).
