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china_cn's avatar
china_cn
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3 years ago
Solved

如何约束altera_reserved_tck以及JTAG的相关信号管脚

我正在使用 Intel-ARRIA 10-GX FPGA Development Kit进行开发。在我一个工程中使用了nios来调用SPI，并且在顶层模块中例化了4个jesd204b的ip核。signaltap中抓取了部分jesd204b的输出信号。 但是在下载nios程序的过程中发现nios下载出错，提示的信息是： verify failed between address 0x0 a...
  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    3 years ago

    Hi,

    I would suggest you set a 10MHz constraint to the altera_reserved_tck pin to constrain this JTAG clock.

    The altera_reserved_tck pin is automatically generated for a design that uses a JTAG accessible module such as the SignalTap logic analyzer or the NIOS II debugger.

    Thank you.

    ​

    ​您好，

    ​​我建议的方案就是您试试把altera_reserved_tck管脚约束设置为10MHz。

    ​这是因为SignalTap Analyzer或NIOS II debugger 引用了JTAG组件, 会自动化地引起altera_reserved_tck管脚.

    谢谢

    ​

    Kelly


KellyJialin_Goh's avatar
KellyJialin_Goh
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,

I would suggest you set a 10MHz constraint to the altera_reserved_tck pin to constrain this JTAG clock.

The altera_reserved_tck pin is automatically generated for a design that uses a JTAG accessible module such as the SignalTap logic analyzer or the NIOS II debugger.

Thank you.

​

​您好，

​​我建议的方案就是您试试把altera_reserved_tck管脚约束设置为10MHz。

​这是因为SignalTap Analyzer或NIOS II debugger 引用了JTAG组件, 会自动化地引起altera_reserved_tck管脚.

谢谢

​

Kelly