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晓孙0002's avatar
晓孙0002
Icon for New Contributor rankNew Contributor
6 years ago

XXX. Sof was downloaded to FPGA, Contains a 5G LDPC IP,i find the signal (sink_ready) always low,

I dowmload a xxx.sofwhich contains a 5G LDPC IP，I confirm the rst_n​ is high，but the 5G LDPC output signal (sink_ready)and (source_ready) is low, I generated xxx.sof is not xxx_time_limited.sof.
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

thanks for your update.

Would you mind to share with me a simple test design which could replicate your observation ie the signals connected to GND and also sink_ready stuck at low in hardware? I would like to look into it to see if can spot any anomaly.

Please feel free to let me know the specific device and devkit (if any) that you are using to replicate the observation?

Please share with me the specific steps that you are taking to replicate the observation or test the design. I would like to see if I can bring up a setup to replicate your observation.

Thank you.