Forum Discussion

New Contributor

7 years ago

Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?

I've a problem running DDR3 HMC on Cyclone V SoC Development Board. I instantiated HMC megafunction in schematic top level file, made mem_ pin assignments, connected pll_ref_clk pin to CLK_BOT1 board...

BoonT_Intel

Frequent Contributor

7 years ago

Hi, If you trace the RTL, you can see the afi_clk is direct connect from the PLL out_clk port.

So, the only reason why no clock is due to PLL is lose lock.

Can you monitor is the PLL_LOCK signal assert?

Forum Discussion

Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?

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