Forum Discussion
MEmel1
New Contributor
New ContributorWhy there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?
I've a problem running DDR3 HMC on Cyclone V SoC Development Board. I instantiated HMC megafunction in schematic top level file, made mem_ pin assignments, connected pll_ref_clk pin to CLK_BOT1 board...
NurAida_A_Intel
Frequent Contributor
Frequent ContributorDear MEmel1,
For first step, I recommend you to generate the board test system example design in https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-soc.html#devkit and compare your design setting with the golden design.
Thanks
Regards,
NAli1
