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Altera_Forum
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12 years ago

What is the polarity of DCLK signal in EPCS16 ?

I am using cyclone iii ep3c25 fpga in which I have designed an sopc system which has altera spi ip. I want to access EPCS16 flash using this SPI. For that, what polarity should i kept for the sclk si...
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Altera_Forum
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12 years ago

I presume this is irrelevant.

EPCS will sample the ASDI input and latch the first bit of the command code when it detects the first DCLK rising edge after nCS has gone low.

Then, if DCLK is normally high, it needs to go low just before starting the command sequence; but this will have no effect, since the EPCS status machine is still inactive, until the next rising edge.