ContributorHi,
I am estimating the DDR4 bandwidth for user application. So, I want to know what is the Data bus efficiency of DDR4 hard controller (full rate) in Arria 10 FPGA. [For example, Although DDR4 is 2400MT/s, but user can not achieve 2400MT/s all the time due to CAS with AL).
With Regards,
HPB
Contributor.
Frequent ContributorHi Sir,
The efficiency is affect by many aspect like traffic pattern, board layout and memory device that you using. Typically, the efficiency is varied from 50-70%. However, for some (inefficient) traffic pattern, it may drop further to below 50%.
Thus, you are encourage to run simulation using your traffic pattern to determine the estimate efficiency.
Also, you may refer to Optimizing Controller Performance chapter of the EMIF User Guide to determine the setting that suit to your traffic pattern.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf#page=415
Hope this helps.
Frequent ContributorI’m hope that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
