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HBhat2's avatar
HBhat2
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5 years ago

What is the Data bus efficiency of DDR4 hard controller in Arria 10 ?

Hi, I am estimating the DDR4 bandwidth for user application. So, I want to know what is the Data bus efficiency of DDR4 hard controller (full rate) in Arria 10 FPGA. [For example, Although DDR4 is 2...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Sir,

The efficiency is affect by many aspect like traffic pattern, board layout and memory device that you using. Typically, the efficiency is varied from 50-70%. However, for some (inefficient) traffic pattern, it may drop further to below 50%.

Thus, you are encourage to run simulation using your traffic pattern to determine the estimate efficiency.

Also, you may refer to Optimizing Controller Performance chapter of the EMIF User Guide to determine the setting that suit to your traffic pattern.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf#page=415

Hope this helps.