Forum Discussion
ShengN_altera
Super Contributor
3 years agoHi,
Mentor® Verification IP – Intel® FPGA Edition (Mentor VIP – Intel FPGA) provides Bus Functional Models (BFMs) that simulate the behavior and facilitate the verification of design IP.
I think are some mentor library files for simulation purpose.
Best Regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.