Forum Discussion
Occasional ContributorWhat happens if a signal value changes during the wait_request assertion?
As long as all your writes completed successfully, that should be OK. Is it a BFM in your simulation saying there is an error?
The interconnect may, at that point, be asserting waitrequest for something else happening in the system. Your host doesn't care anymore because it's done with its transfers.
Occasional ContributorSorry. I should've been more clear.
I was trying to say that after last write, since there is no other write, the mem_en goes down, but this happens exactly when the waitrequest is asserted. That wouldn't have any effect on write transfer, but still I get error in Modelsim saying that control signnals shouldn't change during the time waitrequest is high. So, I just want to make sure there is no problem in the design. It's just a safe error.
Again, thanks for your answers.
