Forum Discussion
Occasional ContributorWhat happens if a signal value changes during the wait_request assertion?
As long as all your writes completed successfully, that should be OK. Is it a BFM in your simulation saying there is an error?
The interconnect may, at that point, be asserting waitrequest for something else happening in the system. Your host doesn't care anymore because it's done with its transfers.
Occasional ContributorThanks for your answer.
What I am doing is performing write transfer for let's say 1000 cycles. I designed my own IP core as the host, which is connected to the on-chip memory with AV_MM interface. mem_en signal is connected to write signal which indicates a valid write transfer. My question is if in the last transfer (1000th write), when waitrequest goes high, the host drives 0 on mem_en (or write signal) afterward, would be any problem? Let's say the mem_en signal was 1 during entire write transfers (for 1000 cycles). I know that agent expects a constant value for all control signals during the time that waitrequest is asserted. But, since this is the last transfer and there would not be any other transfer, would be any problem if I change the control signals (here mem_en or even address) when waitrequest is 1?
Super ContributorOK, that clears it up a little bit. I didn't realize mem_en was your write signal from the host. To answer your question, if the 1000th write has completed (host asserted control signals and waitrequest was low for 1 cycle), then you can do whatever you want. But it sounds like you're saying that waitrequest goes high on that last write, in which case, the last write has not completed yet and the interconnect is telling the host to wait before performing that final write.
Again, I'm not sure I'm interpreting your situation correctly.
