Forum Discussion
Occasional ContributorWhat happens if a signal value changes during the wait_request assertion?
As long as all your writes completed successfully, that should be OK. Is it a BFM in your simulation saying there is an error?
The interconnect may, at that point, be asserting waitrequest for something else happening in the system. Your host doesn't care anymore because it's done with its transfers.
Super ContributorCan you explain the use or design scenario here? waitrequest is the input to a host (previously referred to as a master) in a Platform Designer system (typically) to tell it that an agent (previously referred to as a slave) is not ready to receive or process a read or write command, perhaps due to arbitration in the system interconnect or because the agent needs more time to respond to the command. waitrequest can be controlled manually by an agent or automatically by the system interconnect.
It sounds like you are issuing a write command to an agent that has a register that outputs the mem_en signal you mention. mem_en isn't part of the Avalon interface, so I presume you are controlling this agent which in turn controls mem_en. Are you manually controlling waitrequest back to the host with this agent?
Is that an accurate description of what's going on here? The value of mem_en should not be reliant on waitrequest.
