Forum Discussion

KCMurphy's avatar
KCMurphy
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

What clock sources are allowed for an EMIF reference clock?

I need to generate a 200MHz reference clock for an LPDDR3 EMIF. If I don't have any convenient clock available, how can I generate it on chip? There seems to be an issue with using a PLL output as the reference source of an EMIF.

The Altera-ese that I get in the error description is not particularly helpful. Does this signal have to come externally, or can I generate it somehow internally.

Arria 10 10AX022C3U19I2SG

Quartus Pro 21.3.0

EMIF 19.2

4 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi KCMurphy,


    The EMIF IP need to be driven from a dedicated clock source.

    It's cannot uses the internally generated clock to drive the logic.


    Regards,

    Adzim


  • KCMurphy's avatar
    KCMurphy
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    And that dedicated clock has to be in the same bank as the EMIF block?

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi KCMurphy,


    "And that dedicated clock has to be in the same bank as the EMIF block?"

    • Yes it's must in the same bank as EMIF block


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    We do not receive any further response regarding to this topic. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.