Forum Discussion

New Contributor

6 years ago

Solved

Warning regarding ignored SDC when compiling PCIe design.

I running the compilation of PCIe avalon ST example design and get a lot of warning like below. Please help... Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc

BoonT_Intel
6 years ago
Hi Sir,
These warning can be ignore. See this KDB link: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-intel-arria-10-and-intel-cyclone-10-avalon-st-or-avalon-mm-interface-for-pci-express-ip-example-design-issue-ignored-sdc-constraint-warnings.html

BoonT_Intel

Frequent Contributor

6 years ago

Hi Sir,

These warning can be ignore. See this KDB link: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-intel-arria-10-and-intel-cyclone-10-avalon-st-or-avalon-mm-interface-for-pci-express-ip-example-design-issue-ignored-sdc-constraint-warnings.html

Forum Discussion

Warning regarding ignored SDC when compiling PCIe design.

Recent Discussions

F-Tile xcvr placement on DK-DEV-AGF023FA

MAX10 TSE reference design

Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models