Altera_Forum
Honored Contributor
13 years agoVIP Suite Scaler II Megacore function
Hi Alterians,
My design consists of a Test patter generator followed by a Scaler ii followed by a clocked video output. My aim is to scale down the input resolution (1280*720) to a standard VGA resolution (640*480) to test the capabilities of the core. All my cores are configured on real time with NiosII commands. I am having hard time outputting the correct test pattern onto my std screen. The thing is that it works perfectly when the resolutions are closer to each other. Such as from SVGA 800*600 to 640*480. The problem as it seems is related to stall behavior as specified in ScalerII chapter in VIP Suite Handbook. The output stalls for the time needed to read one or more input lines. Which makes me think to increase the clock between the Test Pattern Gen and the Scaler ii. But SOPC doesn't allow that, and I believe it is a better practice to drive the video datapath component with the same clock, but feed the Clocked output by the clock standard I willing to use. Does anybody have other suggestions of what might be the problem and how to solve it? PS: I have checked some Altera video reference designs and there is always a Frame Buffer placed right before the CVO. Does it help? It seems only for rate conversion.