Well the easiest thing would be for me to see your design but here are some things that worry me.
1 - Are you aware of and properly handling the ready_latency value of 1 on the scaler's avalon streaming ports? This means that when it asserts din_ready, you present valid data on the next clock cycle. Likewise, when you assert dout_ready, it presents valid data on the following clock cycle.
2 - I don't know if the scaler will operate properly without control packets on the input. I think it will use whatever settings you specified in the megawizard but I've never tried it.
3 - My understanding is that the scaler will put control packets on the output regardless of whether or not they are present on the input. If so, you will have to either ignore or remove these.
4 - For video packets going into the scaler, the data accompanying the startofpacket signal must be a value of zero. This is not part of the actual video data but instead a flag to indicate to the scaler that this particular packet is video data. Similarly, the scaler's output will be in the same format.
5 - I think you should have an elastic line buffer (FIFO) between the scaler and your output.
6 - Obviously you can't tie the dout_ready signal on the scaler to vcc. You need to pull the data out as dictated by output timing.
Do any of these sound like things you need to check or are you covering all of this already?
Jake