Honored Contributor
Honored Contributor:) Hi Jake
In answer to your questions 1. Its Scaler V9 and Quartus II v9 2. Cyclone 2 grade 7 3. I can display a static 720x288 RGB Image (16 bit Ram to resampler to colorspace converter to fifo to display, all homemade except the fifo - Altera megafunction fifo) 4. DRAM 16 bit databus running at 100MHz (Homemade controller) 5. Dual Clock fifo..100MHz in 50MHz out 1024 words deep 6. I'm using nearest neighbour at the moment just because it compiles quicker, I've used a 1:1 scale ratio and got a stable image but I need 800x600 7. The output block is homemade running at 50MHz i.e. vga 800x600x72Hz 8. There is no fifo between the scaler and output 9. I dont send any control packets for resolution, I assumed that the Megafunction wizard would've sorted it out..:) 10. Theres nothing in the output path to remove control packets but I only send startofpacket and endofpacket I've included counters in the vga sync generator section to give 1 pulse a pixel before the frame starts and then give another pulse as the frame ends, I detect these pulses and send the startofpacket, endofpacket signals. Then I enable the fifo output and send the 24 bit data to the scaler. The din_ready output of the scaler is checked before any of the above is allowed. I've connected the output enable of the scaler to Vcc and also to a VGA_Active_Area signal, both give the same result. This is the system as it stands at the moment...There have been other manifestations with various different timing scenarios, none of which worked lol Thanks for your response Peter
