Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi JackobJones,
Thanks for the reply! Here are some answers to your questions: 1. Cyclone 3, (EP3C16) 2. The FIFO is 2048 pixels (I need it to work up to HD 1080i which has 1920 pixels per line) 3. I am not aware of suvh a blxo, but I will look again... 4. Yes, I am sure the timing is properly constrained. I have a set_input_delay constraint for all data inputs. I have also registered the input data and placed the registers in the IO blocks. TimeQuest reports a max video clock of 159MHz, where I need only up to 75MHz. I have also analyzed the worst case setup and hold path in Timequest and I can see that it is correct as I expect it. If there was a timing problem, I would have expected noise in the images, or "bad pixels". But if it works, it works 100% until it gets into this funny state, where it does not work at all. 5. Yes, I would like to but I am using an evaluation license for the VIP cores which makes it impossible to signaltap the design (or am I wrong? I am under the impression that I cannot signaltap a design which includes time limited IP evaluation cores). 6. Ah-ha, didn't know that! I'll have a look. I have played around with the vid_locked signal as well bit it made no difference. I do take the vid_locked signal low when my system detects a loss of signal (this is done by a uC which monitors the video decoder). Personally I think it is not a good idea to run the core from the video clock - I would take all data into a FIFO as soon as possible then do all the work in the system clock domain. Since I have no control over the input video clock (it might glitch - violating timing), it would never be safew to run the main control state machines from this clock. I have seen, for instance, that if I remove the video clock, the status register still indicates a lock and valid line and pixel counters (it reads back 0x01f8). This should not be the case - without a video clock, the status should read back that it does not have lock, and this can only be done if the control runs of the system clock. Anyhow, I am on the verge of rewriting this core myself... Thanks again! Niki