Honored Contributor
Honored Contributor1 - Which device family are you using?
2 - How deep did you make the FIFO inside the clocked input block? 3 - Have you checked the box that allows recovery of SD? 4 - Are you certain you have properly constrained timing on the input side of the clocked video input block? Where is the input coming from? (IC, SDI receiver core, etc.). All of the logic inside the CVI block is clocked using the video clock and not the system clock. So all the word and line counters, the VIP control packet insertion, everything is run from that clock. If it's not stable or properly constrained, you'll have problems. Also, I would make sure the "vid_locked" signal is truly getting set to 0 when you remove the video. You might need to add some logic to ensure that it does. 5 - I would signaltap the Avalon streaming interface out of the clocked input block. 6 - I would signaltap the core itself. Unlike the other Video IP cores, you actually have access to the source code for the clocked input block. Look in your database directory (db) for a file called alt_vip_Vid2IS.v or just Vid2IS.v. This is the source code for the clocked input block. I have not seen this particular problem and I have used the core under the same conditions as you (SD/HD/3G video). However, I haven't used it for a while as I long ago wrote my own version of the CVI block. It's possible the Altera version has undergone some changes. Jake
