Altera_Forum
Honored Contributor
14 years agovip clock in and clock out
In my design for connection with the hd_SDI i am using clkin and clkout (vip) back to back and taking my output and feeding to the hd_SDI ip core .
vedio ==> clkin ip ==> clkout ip ==> hd_SDI(ip) data (embedded) (VIP) (VIP) here the issue am facing is am not able to get the output from clkout ip (vip). am using 1080i 60 hz. plz tell me whether my approach is correct or not .