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Altera_Forum's avatar
Altera_Forum
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15 years ago

VIP - simple CTI to ITC always overflow/underflow

I have another question in about a larger VIP design that I was (and am still) working on... but I was making very little progress so I stepped back and did a simple CTI to ITC path through SOPC builder. I also have a Slave SPI to Avalon master in the system that I use to talk to the control ports of the two video devices. I am using QII 10.1 (SP1) and have a 1280 x 1024 signal coming onto my board and into the fpga. I've done many variations of the system and cannot keep the CTI from overflowing it's fifo... and once it overflows the ITC fifo at some point in the not too distant future underflows.. I've tried to impliment the SFO connection between the two modules, but this was unsuccessful.. (I'm not positive that I'm setting up the registers correctly but I think I am)...

Anyway, this is a very simple system and I'm really surprised that I'm having so much trouble getting this to work....

Any guidance or suggestions would be greatly appreciated.

I've got the Video inputs, Avalon stream outputs of the CTI signal tapped along with the Avalon stream inputs and video outputs of the ITC... This system runs a few frames (it seems) and then overflows the CTI and then underflows the ITC and then after a few more seconds comes to a stop.

thanks,

david

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Still struggling with the CTI overflow issue... I've pretty much isolated my problem to the fact that the CTI overflows and then never will drive it's Avalon Stream Data Valid signal high again... Seems like it gets locked up and won't recover...

    My system now consists of CTI, switch, triple frame buffer, polyphase scaler, switch, ITC... I get a good frame or two through and then the CTI locks up. I have it signal tapped and can see that from the read side of the frame buffer out through the ITC continues to work, but the CTI gets locked up.. I see that the ready signal into the CTI is high but the valid signal nevers goes high... I also see that the control packets coming from the CTI are correct but still no valid signal... I can clear the overflow by turning off the CTI, clearing the sticky bit via the control port, but as soon as I turn the CTI back on it almost immediately goes overflow again... At the same time that this is happening I never see the valid signal go high so it is obvious that the input fifo of the CTI overflows again....

    Any help would be appreciated...

    david
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi David,

    What hardware are you targetting? Do you have a project to share that I can take a look at?

    I have used VIP suite quite a bit and may be able to help you as it is generally trouble-free :)

    Regards,

    Steve.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Steve,

    Thanks for the reply... I never did really get the Clocked Video Input to work consistently and so I just wrote my own. That was actually the plan all along but we had originally thought we would get something going very quickly with all VIP modules. We were never successful with that, so I had to start my rewrite earlier than we had originally planned for... net/net is that we are in production and doing very well.. so it all worked out.

    I do still use the VIP de-interlacer and frame-buffer but everything else has been replaced. Input, Output, Clipper, Switch, Pass-through path, DS, US, CSC, SPI Flash frame reader with chroma resampler... The original work was all done in SOPC builder and I am just now finishing up the port to Qsys and parameterizing all the modules with custom tcl scripts.... We will be releasing some firmware feature upgrades soon and the new fpga load will go in with that...

    thanks again for the shout.

    david