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Johnious's avatar
Johnious
Icon for New Contributor rankNew Contributor
3 years ago
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VIP - Communication between Frame buffer and SDRAM

Hello.
I'm new to VIP suite. I would like to design a chain that consists of CVI -> Clipper -> Scaler (Upscale) -> Frame buffer -> CVO.

The frame buffer is needed for frame conversion from 50 Hz to 60 Hz. I have two questions.

1) Which selection should i enable in order to configure the input and output frame rate? run-time writer control, or run-time reader control?

2) I see that the buffer has 2 channels for memory, one for reading and one for writing. How do I manage the controller since the DRAM is single port? Does the buffer request to read and write at the same time or sequentially?

Thanks in advance.

  • Johnious's avatar
    Johnious
    3 years ago

    Thanks for the answer. Eventually the frame buffer worked.

    I used the SDRAM controller IP and I just connected both read and write channels to the controller input, so the platform designer made the necessary arbitration logic.

3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Johnious,


    The Frame Buffer IP has two basic blocks which are Writer and Reader.

    Memory Writer block will receive the input and perform write transfer to memory.

    Memory Reader block will perform read transfer from memory and process it for the output.


    The run-time writer control needs to turn on when the module is Frame Writer Only.

    The run-time reader control needs to turn on when the module is Frame Reader Only.


    The read and write transaction will be done sequentially.

    There is an Arbitration Logic that manage the transaction for fairness-based, round-robin order.

    This protocol will allow equal share for both Read and Write transfer.


    I hope that your questions have been addressed.

    Please let me know if you still have further question on this topic


    Thanks.

    Regards,

    Adzim


    • Johnious's avatar
      Johnious
      Icon for New Contributor rankNew Contributor
      3 years ago

      Thanks for the answer. Eventually the frame buffer worked.

      I used the SDRAM controller IP and I just connected both read and write channels to the controller input, so the platform designer made the necessary arbitration logic.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.